The present invention relates to the field of signal modulation, and more particularly, to an architecture and method for decoding a biphase modulated digital signal using a phase synchronization signal generated from the digital signal.
In many applications, digitized signals or digital data are transmitted through a broadcasting medium on a carrier having frequencies or wavelengths digitally modulated. The digital coding is often based on a biphase modulation, which is also referred to as Manchester coding or Biphase Mark coding. With respect to such a modulation coding scheme, the occurrence of a transition within a given time slot corresponds to a logic xe2x80x9c1xe2x80x9d while the absence of any transition during the time slot corresponds to a logic xe2x80x9c0xe2x80x9d. In each case, there will be a transition at the beginning and another transition at the end of the reference time slot. Therefore, the information content is tied to the presence or absence of transitions from a logic state to a different logic stage during the interval between the start transition. The information content is totally independent from the logic value of the signal, i.e., whether such a signal is high or low during a certain phase.
The received digital stream to be demodulated is then decoded using a synchronizing signal (clock) generated to maintain a perfect phase synchronization with the stream of received digital data. Coding based on a Manchester biphase modulation and the relative signal of an ideal decoding clock are illustrated in FIG. 1. Coding based on the biphase Manchester modulation is used in many applications according to established and standardized protocols. A typical example of an application is with respect to the broadcast of audio signals coded according to the AES-EBU standard. This standard has been enhanced and redefined within different standardization bodies, e.g., SP-DIF, IEC958 and EIAJ. However, the biphase coding has remained unchanged.
In many systems, digital data are organized in a discontinuous manner that is exchanged in bursts. Typical applications include those in which the data is structured according to a TDMA (Time Division Multiple Access) protocol. In a TDMA application, continuity of phase synchronization between successive bursts is not guaranteed. Among these systems, wideband access systems of the passive optical network (PON) type are also included.
For example, when broadcasting digitized audio signals, two samples of the audio signal are transmitted at a prefixed sampling frequency. These two samples relate respectively to the right channel and to the left channel. Each of these samples is associated with a subframe. The subframes of channel A and of channel B are transmitted serially and alternately. Each subframe is preceded by an acknowledgment preamble, as illustrated in FIG. 2.
By way of illustration, an example is taken into consideration. This is done without intending to limit the application of the system of the invention. The ensuing description shall refer to an AES-EBU broadcasting protocol of digitized audio signals for pointing out the significant aspects of the invention. With reference to the scheme of FIG. 2, the pair of subframes A and B corresponding to the same sampling instant forms a frame. A whole set of 192 consecutive frames forms a block.
A subframe contains data relative to the audio sample, and a series of additional information. A subframe structure is represented in FIG. 3. Out of the 32 bits, the first four bits form the preamble. The following four bits transfer auxiliary data. The audio sample is represented by the following twenty bits. The last four bits contain control information, i.e., the validity bit (V), the user bit (U), the state of the channel bit (C) and the parity bit (P), respectively.
There are three different preambles that respectively identify the beginning of the subframe relative to channel A (X preamble), the beginning of the subframe relative to channel B (Y preamble), and the beginning of a new block signaled by the substitution of the X preamble with the Z preamble. FIG. 4 shows the relative waveforms of the three preambles. In addition to the three preamble sequences shown in the figure, the corresponding inverted versions are also valid since the modulation code does not depend on the signal polarity.
For the correct reception and interpretation of the digital stream, it is necessary to have a synchronizing signal that permits the signal to be sampled correctly and to apply the samples to a decoding logic. This phase synchronization signal must have an edge for each possible transition change of the broadcasted signal. Furthermore, the edge of the synchronization signal should fall as close as possible to the middle of the interval between any two possible transition variations to ensure maximum immunity to noise and jitter.
Normally, this phase synchronization signal (clock) is generated by a PLL circuit locked to the switching frequency of the broadcasted signal with a carefully controlled phase. Once the signal is sampled, the decoding logic may be designed as a state machine using the synchronization signal itself as a clock. In this, as well as in other similar applications, the synchronization signal is commonly produced by an analog PLL circuit. The analog PLL circuit extracts from the received signal its clock content using a passband filter, and a VCO is locked to the switching frequency of the received signal to generate a stable clock.
The obtained clock signal is generally used, apart for decoding the data, to drive a D/A converter downstream from the receiver. Therefore, the obtained clock signal must be very stable in terms of jitter to prevent degradation in the performances of the converter. If this function is not required, such as when a DSP is to receive the data, a completely digital approach is preferred to provide reduced integration complexity. A digital approach does not require analog components such as a VCO, filters and frequency comparators.
Furthermore, even in an analog receiver, there exist operating conditions in which the signal is not perfectly locked, i.e., at start up or during switching among different signal sources. In these cases, the receiver would sample the signal at wrong instants causing decoding errors. Normally, a receiver signals these conditions through a validity bit. However, it would be preferable to have an intrinsically more robust receiver capable of correctly interpreting the signal even under a condition of an unlocked clock.
This invention relates primarily to an improved decoding method for an input digital signal or digital stream that is coded according to a biphase modulation. Decoding is performed by sampling the input digital signal with a sampling signal in phase synchronization with the input digital signal. The phase synchronization signal is derived from a clock signal (master clock) having a higher frequency than the maximum switching frequency of the digital input signal. The frequency of the clock signal is divided by a fully digital divider circuit having an irrational or non-integer ratio. The digital divider circuit is self-synchronizing with the input digital signal.
Preferably, the master clock signal should have a frequency in the vicinity of an integer multiple of the maximum frequency of the input signal, i.e., nominally a multiple of the maximum frequency of the input signal. According to one approach, the master clock signal is divided by a certain integer number determined by the use of a divider, while enabling or disabling its switching through control signals. The control signals are generated by two circuits which sample the input signal with the master (high frequency) clock signal and analyze triplets of consecutive sampling values. The first circuit generates a first control signal upon detecting the triplet 001 or 110. The second circuit generates a second control signal upon detecting the triplet 011 or 100.
Preferably, enabling or disabling of the divider by the first circuit takes place on the rising edge of the master clock, and by the second circuit on a falling edge of the master clock. Another aspect of the invention is to provide an architecture of a fully digital frequency divider of an irrational or noninteger ratio that is self-synchronizing with an input digital signal coded according to a biphase modulation. The fully digital frequency divider is capable of generating a sampling signal of the input stream with the characteristics illustrated above. The frequency divider uses a master clock of a sufficiently high frequency, typically a multiple thereof (at least nominally) having a value in the vicinity of a multiple integer of the switching frequency of the input stream, though not necessarily synchronized with it.